26.5 PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability
نویسندگان
چکیده
Leakage control during circuit operation is more challenging than standby mode control due to the short time to deactivate blocks, large overhead energy and run-time leakage variations. This paper proposes circuit techniques that address these challenges to reduce run-time leakage in on-die SRAM caches. A source-biased gated-ground SRAM is proposed; an efficient way to utilize this technique under severe leakage variations exploits the architectural behavior of an L1 cache.
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